1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device that generates an internal voltage.
2. Description of Related Art
In semiconductor devices such as a DRAM (Dynamic Random Access Memory), an internal voltage generating circuit is used to generate an internal voltage from an external power supply voltage. The internal voltage generating circuit includes a differential amplifier having a current mirror circuit, and a driver transistor having a control terminal that is connected to an output terminal of the differential amplifier. An internal voltage that is equivalent to a reference voltage is generated by these elements.
The internal voltage generating circuit is normally configured to be activated only when it is necessary so as to reduce its power consumption. The activation of the internal voltage generating circuit is performed by turning on a current supply transistor that is connected between a common source of a differential amplifier and a grounding wire. When the current supply transistor is turned on, a current flows into the current mirror circuit in the differential amplifier and then the drive transistor is turned on, thereby generating an internal voltage. Examples of such a voltage generating circuit that performs activation control are disclosed in Japanese Patent Applications Laid-open Nos. H5-62481, 2001-84765, and H11-96758.
In recent years, along with the increase in processing speeds of semiconductor devices, the permissible period of time required to stabilize an internal voltage from immediately after activating an internal voltage generating circuit has become very short (hereinafter, the period of time is referred to as “stabilization time of an internal voltage”). As a DRAM is exemplified, in a DLL (Delay Locked Loop) circuit that generates an internal clock signal LCLK for outputting data to outside, the stabilization time of the internal clock signal LCLK (the period of time required to stabilize the internal clock signal LCLK from immediately after activating the internal voltage generating circuit) is only 24 nanoseconds. Therefore, there remains only a shorter time as the stabilization time of an internal voltage VPERD, which is an operation power supply voltage of the DLL circuit.
However, in the conventional semiconductor device described above, there are cases that such a short stabilization time cannot be realized. That is, while the internal voltage generating circuit is configured to be activated at the same time as the semiconductor device is returned from a power-down mode, a circuit that is a supply destination of an internal voltage is also activated at the time. Therefore, current consumption is started immediately after activating the internal voltage generating circuit. However, because the internal voltage generating circuit is not stable immediately after its activation, an output potential of the internal voltage generating circuit is reduced for a while. The reduced output potential is returned to an original level after a certain period of time; however, when the current consumption amount of the supply destination circuit is small, the degree of reduction in the output potential becomes small and thus reaction of a potential of the output terminal of the differential amplifier is slowed, thereby causing a requirement of a long time for the reduced output potential to return to the original level. As a result, the short stabilization time mentioned above cannot be realized.
Consequently, there has been a demand for a technique that enables to stabilize an internal voltage in a short time, regardless of the current consumption amount of a supply destination circuit.